The present invention relates to a MOS type solid state image sensor for use in a digital camera and the like.
FIG. 17 shows an example of a conventional solid state image sensor composed of MOS transistors. This solid state image sensor includes a photosensitive region 14 in which a plurality of amplifying unit pixels are two-dimensionally arranged, and each of the unit pixels includes a photodiode (PD) 1, a read transistor 2, a floating diffusion (FD) portion, a reset transistor 3, a detect transistor 4 and an address transistor 5. The solid state image sensor further includes signal lines 6, drain lines 7, read gate lines 8, reset gate lines 9, address gate lines 10, a vertical shift register 12 for selecting a row of pixels, a horizontal shift register 13 for selecting a column of pixels, and a timing generation circuit 11 for supplying necessary pulses to the shift registers 12 and 13.
Signal charge having been subjected to photoelectric conversion by the PD 1 is read by the read transistor 2 to the FD portion which is a storage region for storing the signal charge. The potential of the FD portion is determined according to the amount of charge thus read to the FD portion, so as to change the gate voltage of the detect transistor 4, and if the address transistor 5 is selected, a signal voltage is taken out onto the signal line 6.
In the conventional solid state image sensor of FIG. 17, each unit pixel includes two lines extending in the vertical direction (namely, the signal line 6 and the drain line 7), three lines extending in the horizontal direction (namely, the read gate line 8, the reset gate line 9 and the address gate line 10) and four transistors (namely, the read transistor 2, the reset transistor 3, the detect transistor 4 and the address transistor 5). However, when pixels are more refined, it is indispensable to reduce the number of lines for improving the numerical aperture of each pixel.
According to a technique disclosed in Japanese Laid-Open Patent Publication No. 10-93070, a gate line used for both read and reset is employed. A read pulse for a given pixel (first pixel) and a reset pulse for another pixel adjacent in the column direction (second pixel) are supplied through the same gate line, and the threshold voltage of the read transistor is set to be higher than the threshold voltage of the reset transistor and a ternary pulse is supplied to the gate line used for both read and reset.